On July 7, 2006 the www.z390.org site published version 1.1.01 which has a significant performace improvement for the open source z390 J2SE Java runtime emulator which increased the speed of the www.mfatc.org MIPS calculation demo by over 50%. The speed increase was achieved by tuning the pz390 emulator code to use 4 smaller table switches to index opcodes instead of one 256 entry switch table for the primary opcode. A new version of the z390 instruction speed caculation contributed by Melvyn Maltz was also published so you can see individual z processor instruction speeds for z390 along with comparison to earlier base line speeds:
http://www.automatedsoftwaretools.com/z390/z390_Benchmark_Instruction_Timing.htm
Saturday, July 08, 2006
Monday, July 03, 2006
www.mfatc.org now has 3 demos in HLASM, HLA, C++, COBOL, and Java
The www.mfatc.org site now has 3 demos in HLASM, HLA, C++, COBOL, and Java which you can download, compile, and execute using free compilers and runtimes available for Windows 2000 and XP in InstallShield format. The demos currently include:
1. HELLO - Display "Hello World"
All 5 source versions only require 4-5 lines of souce code.
2. POWERS - Display powers of 2 from 0 to 31
All 5 demos use structured programming support to perform a loop which calculates and displays each power. The souce code sizes range from 9 lines for C++ to 23 lines for z390 mainframe assembler which does its own packed decimal text formatting for WTO.
3. MIPS - Calculate MIPS rating for simple loop decrementing 32 bit integer until 0
All 5 demos use structured programming support to perform a loop which decrements 32 bit integer until 0 and uses the difference in starting time versus ending time to calculate approximate millions of instructions per second. The lines of source code range from 28 for C++ to 70 for COBOL which required time and date record layouts. The initial results using a Dell 3.05 GHZ Pentium 4 processor running Windows XP are quite revealing:
1. z390 - 0.9 MIPS (This is the slowest due to overhead of mainframe instruction emulation written in Java which compiles to portable virtual machine code.)
2. HLA - 5840 MIPS (I'm amazed that HLA generated ASM code optimized to take maximum advantage of the Pentium 4 hardward pipelining can perform up to 2 instructions per clock cycle. HLA is definitely the language to use for optimizing code speed on Intel hardware.)
3. C++ - 776 MIPS (The ASM code generated by the Visual C++ Express compiler performs 6 instructions with 3 memory fetches resulting in the slower but still impressive MIP rating).
4. COBOL - 68 MIPS (The ASM code generated by the COBOL compiler performs 22 instructions per loop to convert BigIndian integer field in memory to Little Indian format in memory work area to perform decrement and then converts again to store and fetch for compare to zero resulting in the slower speed.)
5. Java - 1430 MIPS (The J2SE Java compiler generated a 4 instruction Java Virtual Macine loop and the J2SE runtime optimized its execution to out perform C++ by almost 2 to 1 which is very impressive).
Now I'm highly motivated to do further research on how to improve the z390 emulation performance and hope to include some initial improvements in the next z390 v1.1.01 release. However even 0.9 MIPS for mainframe execution on your Windows desktop is not bad. Some may remember that PC/370 started at 25,000 instructions per second on a 4 MHZ z80 chip and that was fast enough of a lot of I/O bound applications.
1. HELLO - Display "Hello World"
All 5 source versions only require 4-5 lines of souce code.
2. POWERS - Display powers of 2 from 0 to 31
All 5 demos use structured programming support to perform a loop which calculates and displays each power. The souce code sizes range from 9 lines for C++ to 23 lines for z390 mainframe assembler which does its own packed decimal text formatting for WTO.
3. MIPS - Calculate MIPS rating for simple loop decrementing 32 bit integer until 0
All 5 demos use structured programming support to perform a loop which decrements 32 bit integer until 0 and uses the difference in starting time versus ending time to calculate approximate millions of instructions per second. The lines of source code range from 28 for C++ to 70 for COBOL which required time and date record layouts. The initial results using a Dell 3.05 GHZ Pentium 4 processor running Windows XP are quite revealing:
1. z390 - 0.9 MIPS (This is the slowest due to overhead of mainframe instruction emulation written in Java which compiles to portable virtual machine code.)
2. HLA - 5840 MIPS (I'm amazed that HLA generated ASM code optimized to take maximum advantage of the Pentium 4 hardward pipelining can perform up to 2 instructions per clock cycle. HLA is definitely the language to use for optimizing code speed on Intel hardware.)
3. C++ - 776 MIPS (The ASM code generated by the Visual C++ Express compiler performs 6 instructions with 3 memory fetches resulting in the slower but still impressive MIP rating).
4. COBOL - 68 MIPS (The ASM code generated by the COBOL compiler performs 22 instructions per loop to convert BigIndian integer field in memory to Little Indian format in memory work area to perform decrement and then converts again to store and fetch for compare to zero resulting in the slower speed.)
5. Java - 1430 MIPS (The J2SE Java compiler generated a 4 instruction Java Virtual Macine loop and the J2SE runtime optimized its execution to out perform C++ by almost 2 to 1 which is very impressive).
Now I'm highly motivated to do further research on how to improve the z390 emulation performance and hope to include some initial improvements in the next z390 v1.1.01 release. However even 0.9 MIPS for mainframe execution on your Windows desktop is not bad. Some may remember that PC/370 started at 25,000 instructions per second on a 4 MHZ z80 chip and that was fast enough of a lot of I/O bound applications.
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