Friday, March 21, 2008

Why is a slower MIP rate with new z10 instructions better?


Why is a slower MIP rate with new z10 instructions better? The answer based on the initial results of problem #18 solution posted today on the ZMFACC Mainframe Assembler Coding Contest would appear to be that by using the new compare and branch instruction for z10 replacing 2 separate compare and branch on condition instructions results in a lower MIP rate but a faster execution time. Even though the MIP rate is lower, there are fewer instructions required to do the same work, and the elapsed time required is less. For the solution posted, the MIP rate using z390 on Intel Duo Core 2.1 GHZ processor dropped from 8.7 to 7.3 MIPS or 15%but the elapsed time also dropped from 343 ms to 271 ms or an 8% reduction in elapsed time. To see the source code and execution log output for this solution plus new problem #19 posting visit:

Don Higgins

Friday, March 14, 2008

z390 with 11 new ASSIST and 226 new z10 instructions

You never know what will happen at SHARE. This year SHARE started several new ventures for the z390 project resulting in the release of v1.4.01 today with the following major additions:

1. The ASSIST instructions for simplifying assembler program I/O have been added at the request of Northern Illinois University for use by students in their computer science classes. After installation of z390 v1.4.01 enter the command ASSIST assist\DEMOAST1 for demo.

2. Following IBM's announcement of a new z10 mainframe on February 26 during SHARE, a total of 226 new z10 instructions have been added to z390 for use by students learning about the z10 and for developers wanting unit test code before implementing on the new z10 processors. The new z10 instructions include:

a. Compare and branch - based on z390 testing these appear to be 15% faster than the equivalent compare followed by branch on condition instructions.

b. Move with optional specifications - this instruction which was previously implemented based on preliminary information released at SHARE has been expanded to support lengths greater than 4k.

c. The new translate and test extended instructions now support forword and backward translation for any length with 4 different translate table sizes 256, 512, 64k, and 128k.

d. The new rotate and select bits intructions have been implemented along with an improvement in the speed for existing RLL and RLLG rotate instructions which now use new more efficient shared rotate functions.

Since the new z10 instructions did not include the SQXTR extended decimal floating point square root instructions, the first proto-type millicode z390 version of this instruction has been implemented. To see how SQXTR instruction works, see the DFP solution to the standard deviation contest problem #12. To run the program, enter the command ASMLG mfacc\P12DSH3 after installation of z390 v1.4.01. Also see ZMFACC Mainframe Assembler Coding Contest problem #18 requiring benchmark program for compare and branch on the new z10 mainframe:

Don Higgins